The AD6679 is a 135 MHz bandwidth mixed-signal intermediate frequency (IF) receiver. It consists of two, 14-bit, 500 MSPS analog-to-digital converters (ADCs) and various digital signal processing blocks consisting of four wideband DDCs, an NSR, and VDR monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of sampling wide bandwidth analog signals of up to 2 GHz. The AD6679 is optimized for wide input bandwidth, high sampling rates, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.