Third generation of SHARC processors, which includes ADSP-21262, ADSP-21266, ADSP-21364, and ADSP-21365, offers increased performance, audio-centric peripherals and new memory configurations, including on-chip ROM, that are capable of supporting the latest surround-sound decoder algorithms. All devices are pin-compatible and completely code-compatible with all prior SHARC processors. These newest members of SHARC processor family are based on single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-perfomance audio applications.
Third generation SHARC processors also integrate audio-specific peripherals designed to simplify hardware design and reduce time to market. Grouped together and broadly named digital audio interface (DAI), these functional blocks may be connected to each other or to external pins via software-programmable signal routing unit (SRU). The SRU is innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through SRU include but are not limited to serial ports, SPI ports, an input data port (IDP), precision clock generators (PCG) and timers. This flexibility of resource utilization combined with ease of use of SHARC Processor programming model allow manufacturers to leverage single hardware design for multiple products with varying I/O requirements.